The present invention relates in general to digital circuits for control of cathode ray tube (CRT) displays and particularly to circuits for bit-mapping multi-bit pixel displays.
In a typical bit-mapped, black and white, CRT control system the CRT display is divided into a matrix of pixels and each pixel may be illuminated as necessary to create the desired image on the CRT screen. Each pixel corresponds to a specific bit of a word, stored at a specific address in a random access memory, the pixel being illuminated depending on whether the associated bit is high or low. In a memory having sixteen bit words, information regarding the state of up to sixteen pixels may be stored in each memory location.
In a bit-mapped, color display system, each pixel can take on any of several colors, usually including black and white, requiring more than one bit to describe the color state of each pixel. For instance, in a four bit mapping system, each pixel can be displayed in as many as 16 different colors because there are 16 possible combinations of the four bits describing the pixel. Two methods of storing multi-bit pixel data have been utilized. In a first method, the pixel bits are all stored in the same memory word such that, for instance, a sixteen bit word at a particular memory location may store the bits required to describe four four bit pixels. Thus a single read or write cycle can access or change four four-bit pixels as opposed to sixteen pixels in a single bit per pixel system.
In a second method, each bit of a multi-bit pixel is stored in a separate memory array (or memory "plane") such that in an n-bit per pixel system there are n "overlayed" memory arrays ("planes"), each identical to a single bit per pixel memory array. In this arrangement, assuming sixteen bit words and four bit pixels, the data for a single pixel is stored in four separate memory locations, and four read or write cycles are required to determine or change the color of any one pixel, although 16 pixels are accessed during the four cycles.
These multiple bit-mapped display methods generally involve slower display update times and require longer processing times than single bit per pixel display systems due to the increased number of bits per pixel which must be passed between a processor and a memory array and manipulated by the processor during logical operations. In using either method, it takes about four times longer to update a four bit per pixel display than to update a single bit per pixel display. The display is typically updated by successively writing the pixel data into each plane causing the screen to change several times during each update. The intermediate steps can make the update cycle appear longer to a viewer than when an update occurs in a single step, even if the single step update takes as long as a four step update. Also, whenever the state of any one pixel is to be changed, the controlling processor must ascertain the colors of any other pixels having data sharing the same word in memory. Therefore the processor must read the currently stored word before writing over it. The processor must also read all of the stored pixel data and perform a series of logical operations to determine which pixels are of a particular bit pattern, as for instance, when searching for pixels of a particular color in a bit-mapped color display.